A conventional flash memory is divided into sectors. Each sector includes a large number of memory cells, which are conventionally floating gate devices such as floating gate transistors. Each sector of the conventional flash memory typically includes enough memory cells for one half of a megabyte of storage. Each memory cell includes a gate, a source and a drain. The gate of each memory cell is coupled to a word line. The drain of each memory cell is coupled to a bit line. Typically the drains of five hundred and twelve memory cells are coupled to the same bit line. Each word line and bit line couples only a portion of the memory cells in the sector. Thus, applying a voltage to a word line or a bit line provides the voltage to the gates or drains, respectively, of only the memory cells coupled to the word line or bit line, respectively. Although the gates and drains are coupled to word lines and bit lines, respectively, the sources of all of memory cells in the sector are typically coupled together. Coupling the sources of all of the memory cells in the sector reduces the space required to hold the sector. This reduction of required space is beneficial in flash memory because more memory cells may be placed in a given area. When a voltage is applied to the source of one memory in the sector, the voltage is applied to the sources of all of the memory cells in the sector.
A read operation is performed on conventional flash memories by sensing current. To read a state of a particular memory cell, voltages are applied to the gate, source, and drain of the memory cell. A voltage is applied to the word line coupled to the gate of the memory cell. The source of the memory cell is tied to ground by grounding a line coupled to all of the sources of the memory cells in the sector. A voltage is also applied to the bit line coupled to the drain of the memory cell. The current flowing through the memory cell is then read. The magnitude of the current indicates the state of the memory cell, for example whether the state of the memory cell corresponds to a one or a zero.
Conventional erasing of a memory cell is achieved by applying a relatively high negative voltage to the gate and applying a relatively high positive voltage to the source. Application of these voltages moves charges from the floating gate to the source. Because the sources are tied together, a large positive voltage is applied to all of the sources in the sector. After these voltages are applied, the memory cell is read to ensure that the erasure is complete. If erasure is not complete, then the error introduced by the incomplete erasure will be corrected.
Conventional memory cells may have a leakage current between the source and the drain. This leakage current may flow through the source when no voltage is applied to the gate of the memory cell and could affect reading of another memory cell. When grounding the source of the memory cell being read, the sources of all of the memory cells in the sector are grounded. A voltage is also applied to the drains all memory cells coupled to the same bit line as the memory cell being read. As a result, five hundred and eleven memory cells which are not selected for reading but share the same bit line as the memory cell selected for reading are coupled to ground in parallel with the selected memory cell. The leakage current from the non-selected memory cells may, therefore, combine with the read current due to the memory cell to be read. This phenomenon may result in false readings of the memory cell being read. In addition, when a memory cell is checked during an erase, the leakage currents from five hundred and eleven non-selected memory cells sharing the same bit line as the memory cell being checked may cause false readings which incorrectly indicate that the memory cell has not been erased. This apparent error in erasure of the memory cell will be corrected, increasing the time required to properly erase the memory cell.
Accordingly, what is needed is a system and method for reducing the leakage current due to non-selected memory cells, allowing more accurate read and larger sector sizes. The present invention addresses such a need.